A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having memory cells capable of utilizing the direct tunneling phenomenon and its manufacture method.
B) Description of the Related Art
There have been strong demands for multi functional semiconductor devices which integrate logic circuits and memory cells. A logic circuit is often made of CMOS circuits. It is desired to form both CMOS transistors and memory cells by common manufacture processes as much as possible. There is an increasing demand for memory cells to form random access memories (RAM) among others.
Although a static (S) RAM has a strong compatibility with logic circuit processes, it occupies a large area. A dynamic (D) RAM requires a capacitor, and a recent micro capacitor has a complicated structure resulting in a large increase in cost. Novel nonvolatile memories such as ferroelectric memories, magnetic memories and phase change memories require involvement of new materials, have an insufficient compatibility with logic circuit processes, and are high in cost.
A flash memory has the lamination structure of a floating gate electrode of polysilicon, an inter-poly (inter-electrode) insulating film and a control gate electrode of polysilicon, respectively stacked on a gate insulating film. The flash memory has a good compatibility with logic processes, occupies a small area and can be manufactured at low cost.
FIG. 11A is a schematic diagram showing the structure of a flash memory. On a p-type region of a silicon substrate 100, a tunnel insulating film 101 is formed, for example, by a thermal oxide film having a thickness of 8 nm. On the tunnel insulating film, a floating gate (FG) electrode 102 of polysilicon, an inter-poly (inter-electrode) insulating film 103 and a control gate (CG) electrode 104 of polysilicon are stacked and patterned in the same plan shape. The side walls of the polysilicon are covered with a thermal oxide film 105, and side wall spacers 106 of silicon oxide or the like are formed on the thermal oxide films. On both sides of the stacked gate electrode, high concentration n-type source/drain regions 108 and 110 and shallow n-type extension regions 107 and 109 are formed. The high concentration n-type region 108 and n-type extension region 107 are collectively called a source S. The high concentration n-type region 110 and n-type extension region 109 are collectively called a drain D.
In a write operation, a ground potential is applied to the source S, and a positive polarity high voltage is applied to the drain D and control gate CG. Electrons travel from the source S toward the drain D, and take a hot state due to a high electric field. Since the control gate CG is applied with a positive polarity high voltage, hot carriers receive an upward acceleration, tunnel through the tunnel insulating film, and are injected into the floating gate FG.
Channel hot electrons (CHE) are injected in this manner. Information is stored by the charges accumulated in the floating gate FG. The floating gate FG covered with the insulating films has a charge retention function and constitutes a nonvolatile memory. In erasing the stored information, a negative polarity high voltage is applied to the control gate CG so that Fowler-Nordheim (FN) current flows through the tunnel insulating film 101 and carriers (electrons) are pulled out.
The tunneling oxide film of a flash memory is deteriorated because carriers of hot electrons are injected into the floating gate FG in the state that a high voltage is applied to the tunnel oxide film and because electrons are tunneled through the tunnel oxide film by applying a very high voltage. Endurance against the write/erase cycles is about 105 times. Since the number of rewrite operations is limited although information can be rewritten, the use of this flash memory is limited to a ROM-like device. The write process of channel hot electrons has the poor injection efficiency so that a consumption power increases. Since an erase process uses the Fowler-Nordheim (FN) tunneling phenomenon, a high electric field is required although it provides the high injection efficiency, and an erase speed is very slow as compared to a write speed. As described above, a flash memory has several problems.
A direct tunneling memory (DTM) has been proposed which has a good compatibility with logic processes and a floating gate electrode structure made of a lamination of a polysilicon layer and an insulating layer similar to the flash memory. The direct tunneling memory is a memory having a thin tunnel insulating film allowing carriers directly tunneling through the film.
FIG. 11B is a schematic diagram showing an example of the structure of a direct tunneling memory. On the surface of a p-type region of a silicon substrate 100, a tunnel insulating film 111 is formed by a thermal oxide film having a thickness of 3 nm or thinner allowing carriers to directly tunnel through the film. On the tunnel insulating film, a floating gate electrode 112 of polysilicon is formed and patterned. The upper surface of the floating gate electrode 112 is covered with an insulating film 115. The side walls of the floating gate is covered with an insulating film 113 on which control gate electrodes 114 of n-type polysilicon are formed facing each other.
Under the control gate electrodes 114 and insulating films 113, high concentration n-type source/drain regions 118 and 120 with n-type extensions 117 and 119 are formed. The control gate electrode 114 faces the silicon surface via a relatively thick gate insulating film 113. Insulating side wall spacers 116 are formed on the side walls of the control gate electrodes 114.
In a write operation, a positive high voltage is applied to the control gate CG. Because of capacitive coupling, a voltage is also applied to the floating gate FG so that an electric field is applied to the tunnel insulating film. A channel connected to the source (S) and drain (D) is induced under the control gates CG and floating gate FG. Carriers (electrons) can reach under the floating gate from the source S/drain D to the channel. Since the tunnel insulating film 111 under the floating gate FG is very thin, a high speed write operation by electron direct tunneling can be performed at a low voltage and a low consumption power relative to the flash memory.
As the voltage applied to the control gate CG is released, the channel extinguishes. The extensions 117 and 119 of the source/drain are not overlapped with the floating gate FG and are distracted sideways. It is therefore possible to suppress the leak current from the floating gate electrode.
As a voltage equal to or higher than a threshold value for inducing a channel is applied to the control gate CG and a forward bias is applied to the drain D, the path between the source S and drain D becomes conductive depending upon the charge state of the floating gate FG so that the stored information can be read. If electrons (negative charges) are not accumulated in the floating gate FG, the channel is induced also under the floating gate FG so that the path between the source S and drain D of the transistor turns on. If negative charges are accumulated in the floating gate and the forward bias is cancelled out, the channel under the floating gate FG is extinguished so that the path between the source S and drain D of the transistor turns off.
In erasing the information, a negative high voltage is applied to the control gate. Negative charges (electrons) in the floating gate receive a repulsion force, tunnel through the tunnel insulating film 111 and pulled out into the substrate 100.
In the structure shown in FIG. 11B, the thin tunnel insulating film having a thickness of 3 nm or thinner separates the floating gate electrode 112 from the channel region in the silicon substrate. Since the insulating film 111 is very thin, the charge retention characteristics of the floating gate electrode 112 are deteriorated. In order to hold the information stored in the floating gate even if the transistor becomes volatile, a refresh operation is performed similar to a DRAM. By using direct tunneling, the tunnel insulating film is suppressed from being deteriorated and the endurance characteristics improve greatly. It is therefore possible to use it as a RAM.
Refer to JP-A-2000-150680, U.S. Pat. No. 6,195,292 and “Advantage of a quasi-nonvolatile memory with ultra thin oxide” SSDM2001, p. 532(2001) by T. Usuki, N. Horiguchi and T. Futatsugi, which are incorporated herein by reference.
Although a direct tunneling memory has a bright future, forming the control gates on the side walls degrades the integrity with logical transistor manufacture processes. Furthermore, in the state that the drain current is detected by turning on the select transistor which discriminates the charge state of the floating gate, the channel is induced at least under the control gate so that charges are likely to be injected into the floating gate.